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? semiconductor components industries, llc, 2014 november, 2014 ? rev. 14 1 publication order number: mc14536b/d mc14536b programmable timer the mc14536b programmable timer is a 24?stage binary ripple counter with 16 stages selectable by a binary code. provisions for an on?chip rc oscillator or an external clock are provided. an on?chip monostable circuit incorporating a pulse?type output has been included. by selecting the appropriate counter stage in conjunction with the appropriate input clock frequency, a variety of timing can be achieved. features ? 24 flip?flop stages ? will count from 2 0 to 2 24 ? last 16 stages selectable by four?bit select code ? 8?bypass input allows bypassing of first eight stages ? set and reset inputs ? clock inhibit and oscillator inhibit inputs ? on?chip rc oscillator provisions ? on?chip monostable output provisions ? clock conditioning circuit permits operation with very long rise and fall times ? test mode allows fast test sequence ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free and are rohs compliant maximum ratings (voltages referenced to v ss ) rating symbol value unit dc supply voltage range v dd ?0.5 to +18.0 v input or output voltage range (dc or transient) v in , v out ?0.5 to v dd + 0.5 v input or output current (dc or transient) per pin i in , i out 10 ma power dissipation per package (note 1) p d 500 mw ambient temperature range t a ?55 to +125 c storage temperature range t stg ?65 to +150 c lead temperature, (8?second soldering) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. temperature derating: ?d/dw? packages: ?7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ordering information soic?16 wb dw suffix case 751g marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb?free package 1 1 14536b awlywwg soeiaj?16 f suffix case 966 mc14536b alywg 1 1 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 d decode osc inh mono?in v dd a b c out 1 in 1 reset set v ss clock inh 8?bypass out 2 soic?16 wb soeiaj?16 1 tssop?16 dt suffix case 948f tssop?16 14 536b alyw 1 16 (note: microdot may be in either location)
mc14536b http://onsemi.com 2 stages 9 thru 24 q 24 q 23 q 22 q 21 q 20 q 19 q 18 q 17 q 16 q 15 q 14 q 13 q 12 q 11 q 10 q 9 decoder monostable multivibrator decode out 13 mono-in15 d12 c11 b10 a9 v dd = pin 16 v ss = pin 8 stages 1 thru 8 8 bypass set reset clock inh. 7216 5 out 2 4 out 1 3 in 1 osc. inhibit14 figure 1. block diagram function table in 1 set reset clock inh osc inh out 1 out 2 decode out 0 0 0 0 no change 0 0 0 0 advance to next state x 1 0 0 0 0 1 1 x 0 1 0 0 0 1 0 x 0 0 1 0 ? ? no change x 0 0 0 1 0 1 no change 0 0 0 0 x 0 1 no change 1 0 0 0 advance to next state x = don?t care
mc14536b http://onsemi.com 3 electrical characteristics (voltages referenced to v ss ) characteristic symbo l v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? level v in = v dd or 0 v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc ?1? level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) pins 4 & 5 (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 ?1.2 ?0.25 ?0.62 ?1.8 ? ? ? ? ?1.0 ?0.25 ?0.5 ?1.5 ?1.7 ?0.36 ?0.9 ?3.5 ? ? ? ? ?0.7 ?0.14 ?0.35 ?1.1 ? ? ? ? madc (v oh = 2.5 vdc) source (v oh = 4.6 vdc) pin 13 (v oh = 9.5 vdc) (v oh = 13.5 vdc) 5.0 5.0 10 15 ?3.0 ?0.64 ?1.6 ?4.2 ? ? ? ? ?2.4 ?0.51 ?1.3 ?3.4 ?4.2 ?0.88 ?2.25 ?8.8 ? ? ? ? ?1.7 ?0.36 ?0.9 ?2.4 ? ? ? ? madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.010 0.020 0.030 5.0 10 20 ? ? ? 150 300 600 adc total supply current (note 3, 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (1.50 a/khz) f + i dd i t = (2.30 a/khz) f + i dd i t = (3.55 a/khz) f + i dd adc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.003.
mc14536b http://onsemi.com 4 switching characteristics (note 5) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (note 6) max unit output rise and fall time (pin 13) t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time clock to q1, 8?bypass (pin 6) high t plh , t phl = (1.7 ns/pf) c l + 1715 ns t plh , t phl = (0.66 ns/pf) c l + 617 ns t plh , t phl = (0.5 ns/pf) c l + 425 ns t plh , t phl 5.0 10 15 ? ? ? 1800 650 450 3600 1300 1000 ns clock to q1, 8?bypass (pin 6) low t plh , t phl = (1.7 ns/pf) c l + 3715 ns t plh , t phl = (0.66 ns/pf) c l + 1467 ns t plh , t phl = (0.5 ns/pf) c l + 1075 ns t plh , t phl 5.0 10 15 ? ? ? 3.8 1.5 1.1 7.6 3.0 2.3 s clock to q16 t phl , t plh = (1.7 ns/pf) c l + 6915 ns t phl , t plh = (0.66 ns/pf) c l + 2967 ns t phl , t plh = (0.5 ns/pf) c l + 2175 ns t plh , t phl 5.0 10 15 ? ? ? 7.0 3.0 2.2 14 6.0 4.5 s reset to q n t phl = (1.7 ns/pf) c l + 1415 ns t phl = (0.66 ns/pf) c l + 567 ns t phl = (0.5 ns/pf) c l + 425 ns t phl 5.0 10 15 ? ? ? 1500 600 450 3000 1200 900 ns clock pulse width t wh 5.0 10 15 600 200 170 300 100 85 ? ? ? ns clock pulse frequency (50% duty cycle) f cl 5.0 10 15 ? ? ? 1.2 3.0 5.0 0.4 1.5 2.0 mhz clock rise and fall time t tlh , t thl 5.0 10 15 no limit ? reset pulse width t wh 5.0 10 15 1000 400 300 500 200 150 ? ? ? ns 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14536b http://onsemi.com 5 pin descriptions inputs set (pin 1) ? a high on set asynchronously forces decode out to a high level. this is accomplished by setting an output conditioning latch to a high level while at the same time resetting the 24 flip?flop stages. after set goes low (inactive), the occurrence of the first ne gative clock transition on in 1 causes decode out to go low. the counter?s flip?flop stages begin counting on the second negative clock transition of in 1 . when set is high, the on?chip rc oscillator is disabled. this allows for very low?power standby operation. reset (pin 2) ? a high on reset asynchronously forces decode out to a low level; all 24 flip?flop stages are also reset to a low level. like the set input, reset disables the on?chip rc oscillator for standby operation. in 1 (pin 3) ? the device?s internal counters advance on the negative?going edge of this input. in 1 may be used as an external clock input or used in conjunction with out 1 and out 2 to form an rc oscillator. when an external clock is used, both out 1 and out 2 may be left unconnected or used to drive 1 lsttl or several cmos loads. 8?bypass (pin 6) ? a high on this input causes the first 8 flip?flop stages to be bypassed. this device essentially becomes a 16?stage counter with all 16 stages selectable. selection is accomplished by the a, b, c, and d inputs. (see the truth tables.) clock inhibit (pin 7) ? a high on this input disconnects the first counter stage from the clocking source. this holds the present count and inhibits further counting. however, the clocking source may continue to run. therefore, when clock inhibit is brought low, no oscillator startup time is required. when clock inhibit is low, the counter will start counting on the occurrence of the first negative edge of the clocking source at in 1 . osc inhibit (pin 14) ? a high level on this pin stops the rc oscillator which allows for very low?power standby operation. may also be used, in conjunction with an external clock, with essentially the same results as the clock inhibit input. mono?in (pin 15) ? used as the timing pin for the on?chip monostable multivibrator. if the mono?in input is connected to v ss , the monostable circuit is disabled, and decode out is directly connected to the selected q output. the monostable circuit is enabled if a resistor is connected between mono?in and v dd . this resistor and the device?s internal capacitance will determine the minimum output pulse widths. with the addition of an external capacitor to v ss , the pulse width range may be extended. for reliable operation the resistor value should be limited to the range of 5 k to 100 k and the capacitor value should be limited to a maximum of 1000 pf. (see figures 4, 5, 6, and 11). a, b, c, d (pins 9, 10, 11, 12) ? these inputs select the flip?flop stage to be connected to decode out. (see the truth tables.) outputs out 1 , out 2 (pin 4, 5) ? outputs used in conjunction with in 1 to form an rc oscillator. these outputs are buffered and may be used for 2 0 frequency division of an external clock. decode out (pin 13) ? output function depends on configuration. when the monostable circuit is disabled, this output is a 50% duty cycle square wave during free run. test mode the test mode configuration divides the 24 flip?flop stages into three 8?stage sections to facilitate a fast test sequence. the test mode is enabled when 8?bypass, set and reset are at a high level. (see figure 9.) truth tables input stage selected for decode out 8?bypass d c b a 0 0 0 0 0 9 0 0 0 0 1 10 0 0 0 1 0 11 0 0 0 1 1 12 0 0 1 0 0 13 0 0 1 0 1 14 0 0 1 1 0 15 0 0 1 1 1 16 0 1 0 0 0 17 0 1 0 0 1 18 0 1 0 1 0 19 0 1 0 1 1 20 0 1 1 0 0 21 0 1 1 0 1 22 0 1 1 1 0 23 0 1 1 1 1 24 input stage selected for decode out 8?bypass d c b a 1 0 0 0 0 1 1 0 0 0 1 2 1 0 0 1 0 3 1 0 0 1 1 4 1 0 1 0 0 5 1 0 1 0 1 6 1 0 1 1 0 7 1 0 1 1 1 8 1 1 0 0 0 9 1 1 0 0 1 10 1 1 0 1 0 11 1 1 0 1 1 12 1 1 1 0 0 13 1 1 1 0 1 14 1 1 1 1 0 15 1 1 1 1 1 16
mc14536b http://onsemi.com 6 logic diagram stages 18 thru 23 24 17 stages 10 thru 15 16 t 9 stages 2 thru 7 8 t 1 6 2 reset 8-bypass 14 osc inhibit 3 in 1 4 out 1 out 2 5 set 1 7 clock inhibit r en c s q a9 b10 c11 d12 decoder decoder out 13 15 mono-in v dd = pin 16 v ss = pin 8
mc14536b http://onsemi.com 7 figure 2. rc oscillator stability figure 3. rc oscillator frequency as a function of r tc and c r s = 0, f = 10.15 khz @ v dd = 10 v, t a = 25 c r s = 120 k , f = 7.8 khz @ v dd = 10 v, t a = 25 c r tc = 56 k , c = 1000 pf v dd = 15 v 10 v 5.0 v 8.0 4.0 0 -4.0 -8.0 -12 -16 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c)* *device only. frequency deviation (%) typical rc oscillator characteristics (for circuit diagram see figure 12 in application) 100 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 1.0 k 10 k 100 k 1.0 m 0.0001 0.001 0.01 0.1 r tc , resistance ( ) c, capacitance ( f) f, oscillator frequency (khz) f as a function of c (r tc = 56 k ) (r s = 120 k) f as a function of r tc (c = 1000 pf) (r s 2r tc ) v dd = 10 v figure 4. typical c x versus pulse width @ v dd = 5.0 v figure 5. typical c x versus pulse width @ v dd = 10 v 100 0.1 1.0 10 1000 100 10 1.0 c x , external capacitance (pf) , pulse width ( t w s) r x = 100 k 50 k 10 k 5 k t a = 25 c v dd = 5 v formula for calculating t w in microseconds is as follows: t w = 0.00247 ? r x ? (c x ) 0.85 where r is in k , c x in pf. 1000 100 10 1.0 c x , external capacitance (pf) 100 0.1 1.0 10 , pulse width ( t w s) formula for calculating t w in microseconds is as follows: t w = 0.00247 ? r x ? (c x ) 0.85 where r is in k , c x in pf. r x = 100 k 50 k 10 k 5 k t a = 25 c v dd = 10 v figure 6. typical c x versus pulse width @ v dd = 15 v 1000 100 10 1.0 c x , external capacitance (pf) 100 0.1 1.0 10 , pulse width ( t w s) formula for calculating t w in microseconds is as follows: t w = 0.00247 ? r x ? (c x ) 0.85 where r is in k , c x in pf. r x = 100 k 50 k 10 k 5 k t a = 25 c v dd = 15 v monostable characteristics (for circuit diagram see figure 11 in application)
mc14536b http://onsemi.com 8 figure 7. power dissipation test circuit and waveform figure 8. switching time test circuit and waveforms v dd 0.01 f ceramic 500 f i d c l c l c l v ss pulse generator set reset 8-bypass in 1 c inh mono-in osc inh c b a d out 1 out 2 decode out 20 ns 20 ns 90% 10% 50% 50% duty cycle pulse generator set reset 8-bypass in 1 c inh mono-in osc inh c b a d out 1 out 2 decode out c l v ss v dd 20 ns 20 ns 50% in 1 t wl t wh 50% t phl 90% 10% t plh t tlh t thl out functional test sequence test function (figure 9) has been included for the reduction of test time required to exercise all 24 counter stages. this test function divides the counter into three 8?stage sections and 255 counts are loaded in each of the 8?stage sections in parallel. all flip?flops are now at a ?1?. the counter is now returned to the normal 24?stages in series configuration. one more pulse is entered into in 1 which will cause the counter to ripple from an all ?1? state to an all ?0? state. figure 9. functional test circuit v dd v ss pulse generator set reset 8-bypass in 1 c inh mono-in osc inh c b a d out 1 out 2 decode out functional test sequence inputs outputs comments in 1 set reset 8?bypass decade out q1 thru q24 all 24 stages are in reset mode. 1 0 1 1 0 1 1 1 1 0 counter is in three 8 stage sections in parallel mode. 0 1 1 1 0 first ?1? to ?0? transition of clock. 1 0 ? ? ? 1 1 1 255 ?1? to ?0? transitions are clocked in the counter. 0 1 1 1 1 the 255 ?1? to ?0? transition. 0 0 0 0 1 counter converted back to 24 stages in series mode. set and reset must be connected together and simultaneously go from ?1? to ?0?. 1 0 0 0 1 in 1 switches to a ?1?. 0 0 0 0 0 counter ripples from an all ?1? state to an all ?0? state.
mc14536b http://onsemi.com 9 note: when power is first applied to the device, decode out can be either at a high or low state. on the rising edge of a set pulse the output goes high if initially at a low state. the output remains high if initially at a high state. because clock inh is he ld high, the clock source on the input pin has no effect on the output. once clock inh is taken low, the output goes low on the first negative clock transition. the output returns high depending on the 8?bypass, a, b, c, and d inputs, and the clock input period. a 2 n frequency division (where n = the number of stages selected from the truth table) is obtainable at decode out. a 2 0 ?divided output of in 1 can be obtained at out 1 and out 2 . figure 10. time interval configuration using an external clock, set, and clock inhibit functions (divide?by?2 configured) pulse gen. pulse gen. clock 8-bypass a b c d reset osc inh mono-in set clock inh in 1 v ss decode out out 2 out 1 8 16 +v 6 9 10 11 12 2 14 15 1 7 313 5 4 decode out clock inh set in 1 powerup v dd
mc14536b http://onsemi.com 10 figure 11. time interval configuration using an external clock, reset, and output monostable to achieve a pulse output (divide?by?4 configured) note: when power is first applied to the device with the reset input going high, decode out initializes low. bringing the reset input low enables the chip?s internal counters. after reset goes low, the 2 n /2 negative transition of the clock input causes decode out to go high. since the mono?in input is being used, the output becomes monostable. the pulse width of the output is dependent on the external timing components. the second and all subsequent pulses occur at 2 n x (the clock period) intervals where n = the number of stages selected from the truth table. pulse gen. clock 8-bypass a b c d reset set clock inh mono-in osc inh in 1 v ss decode out out 2 out 1 8 16 +v 6 9 10 11 12 2 1 7 15 14 313 5 4 decode out reset in 1 powerup v dd r x c x *t w .00247 ? r x ? c x 0.85 t w in sec r x in k c x in pf *t w
mc14536b http://onsemi.com 11 figure 12. time interval configuration using on?chip rc oscillator and reset input to initiate time interval (divide?by?2 configured) note: this circuit is designed to use the on?chip oscillation function. the oscillator frequency is determined by the external r and c components. when power is first applied to the device, decode out initializes to a high state. because this output is tied directly to the osc inh input, the oscillator is disabled. this puts the device in a low?current standby condition. the rising edge of t he reset pulse will cause the output to go low. this in turn causes osc inh to go low. however, while reset is high, the oscillator is still disabled (i.e.: standby condition). after reset goes low, the output remains low for 2 n /2 of the oscillator?s period. after the part times out, the output again goes high. pulse gen. 8-bypass a b c d reset osc inh mono-in set clock inh in 1 v ss decode out out 2 out 1 8 16 +v 6 9 10 11 12 2 14 15 1 7 313 5 4 v dd r s r tc c out 2 out 1 reset powerup r s f r c decode out t w r tc = hz = ohms = farads f osc 1 2.3 r tc c
mc14536b http://onsemi.com 12 ordering information device package shipping ? mc14536bdwg soic?16 wb (pb?free) 47 units / rail nlv14536bdwg* soic?16 wb (pb?free) 47 units / rail MC14536BDWR2G soic?16 wb (pb?free) 1000 / tape & reel nlv14536bdwr2g* soic?16 wb (pb?free) 1000 / tape & reel nlv14536bdtr2g* (in development) tssop?16 (pb?free) 2500 / tape & reel mc14536bfelg soeiaj?16 (pb?free) 2000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc14536b http://onsemi.com 13 package dimensions soic?16 wb case 751g?03 issue d d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7 11.00 16x 0.58 16x 1.62 1.27 dimensions: millimeters 1 pitch soldering footprint
mc14536b http://onsemi.com 14 package dimensions tssop?16 case 948f issue b ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc14536b http://onsemi.com 15 package dimensions soeiaj?16 case 966 issue a h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc14536b/d eclinps is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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